FPGAs with Multidimensional Switch Topology

Two-dimensional field programmable gate arrays (2DFPGAs) have been hindered by performance degradation caused by the increase in wire area due to high integration. Studies of the 3D-FPGA are in progress to solve this problem [1]–[3]. A 3D-FPGA allows remarkable reduction of routing areas because of the shorter distance between basic blocks to be connected. It is noteworthy that performance degradation of an FPGA is attributable not to the metal wire but mainly to routing switches. The effect of three-dimensional implementation of an FPGA is presumed as follows: 3D-FPGAs have realized improvement in performance not with the 3D integration technology but with 3D-switch topology. This study proposes implementation of an FPGA by embedding a 3D-FPGA switch topology onto a two-dimensional chip. Furthermore, we propose implementing an FPGA by embedding an FPGA switch topology of four or more dimensions onto a two-dimensional chip. Thereby, switch topology is considered to be effective. Section 2 describes the effectiveness of this multidimensional topology in terms of logic density. Section 3 explains the procedure to embed a multi-dimensional topology onto a two-dimensional chip and demonstrates that the metal wire density does not cause severe problems.